1. Field of the Invention
The present invention relates to a data processor for applying pipe-line processing to various data and a method of controlling the same, and more specifically to improvement of a processor provided with a copy function for making a data processing speed high at a time of a branch instruction.
2. Description of the Related Art
Techniques such as a pipe-line processing system and parallel execution of a plurality of instructions have been used frequently in recent years in a data processor such as a microprocessor in order to improve the performance.
According to these techniques, if there is a gap between a present instruction and a next instruction when an instruction is executed by pipe-line processing, data processing performance is lowered. Therefore, consideration is given so that an instruction supply through a pipe-line is not stopped by providing an instruction prefetch buffer with the processor concerned.
Here, the related art of the present invention will be described. For example, a data processor provided with a copy register for making the data processing speed at time of branch instruction high is composed of an instruction buffer 1, an execution controller 2, an instruction prefetch controller 3, an arithmetic and logical unit (hereinafter referred to as an ALU) 4, a general register 5, a temporary register 6, a copy register 7, another arithmetic and logical unit (hereinafter referred to as an ALU) 8 and another register 9, as shown in FIG. 1.
The copy register 7 always copies the address data 40 be the same as the address data of a register having a specific number in the general register 5 and holds them. Here, it is assumed that the specific number is GR3. The temporary register 6 holds data outputted to a read port of the general register 5 temporarily.
The function of the data processor concerned is such that, when the instruction stored in the instruction buffer 1 is fetched to the execution controller 2, the instruction code thereof is decoded by the execution controller 2, and the outputs of the ALU 4, the general register 5, the temporary register 6 and the GR3 copy register 7 are controlled based on the result of decoding of the instruction code. For example, when the branch instruction (hereinafter referred to also as a jump instruction) is executed, the data fetched from the general register 5 are outputted to an instruction address bus through the temporary register 6 so as to fetch the branch instruction when a branch address is designated in the general register 5 having a specific number, However, the branch address is read out of the copy register 7 and the jump instruction is executed based on the data.
Further, a branch address corresponding to a program counter is computed in the ALU 8, and the result is held in another register 9.
This is aimed at not stopping the instruction supply through the pipe-line of the processor concerned so as to achieve a high data processing speed at time of branch instruction.